Semiconductor device and method for manufacturing the same

ABSTRACT

Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the underlying insulating film and a second overlap portion which overlaps the depression, and a third semiconductor portion disposed between the first and second semiconductor portions and having a portion disposed above the depression, wherein overlap width of the first overlap portion and overlap width of the second overlap portion are equal to each other, a gate electrode including a first electrode portion covering upper and side surfaces of the third semiconductor portion and a second electrode portion formed in the depression, and a gate insulating film interposed between the semiconductor structure and the gate electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2003-407367, filed Dec. 5, 2003,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor device and a method formanufacturing the same.

2. Description of the Related Art

MIS transistors are miniaturized and the gate lengths (channel lengths)thereof are made shorter. As the channel length becomes shorter, apunch-through phenomenon more easily tends to occur between the sourceand drain, and degradation of the transistor characteristic, forexample, an increase in the leakage current will be caused.

In order to solve the above problem, a MIS transistor (Gate-All-Aroundstructure MIS transistor) having an island-form semiconductor structureformed with a rectangular parallelepiped form on a substrate andsurrounded by a gate electrode is proposed in a document 1 (J. P.Colinge et al., “SILICON-ON-INSULATOR ‘GATE-ALL-AROUND DEVICE’”, IEDM1990, 25. 4, pp. 595-598). The MIS transistor is formed as follows.First, an island-form semiconductor structure is formed on a buriedoxide film (BOX film). Then, the buried oxide film is etched by the useof a photoresist mask to form a cavity in a region directly under achannel forming region of the island form semiconductor structure and aregion around the above region. Next, a gate electrode material film isformed on the entire surface containing the cavity and the gateelectrode material film is patterned to form a gate electrode whichcrosses the island-form semiconductor structure. Thus, the gateelectrode which surrounds the channel forming region of the island-formsemiconductor structure is formed. Since the island-form semiconductorstructure also functions as an etching mask when the gate electrodematerial film is patterned, the gate electrode is formed to haveextension portions in the cavity under the source and drain regions.

However, in the above proposal, the cavity and gate electrode are formedby the use of lithography technology. In lithography technology, sincean alignment error occurs, a gate electrode pattern will be formed inposition shifted from the center of the cavity pattern. As a result, thewidth of the extension portion of the gate electrode which lies underthe source region becomes greatly different from the width of theextension portion thereof lying under the drain region. Therefore, onlyone of the overlap capacitance between the gate and source and theoverlap capacitance between the gate and drain becomes larger, having abad effect on the characteristic of the MIS transistor. Further, it isnecessary to form a cavity pattern of large size when taking a marginfor the alignment error into consideration and this leads to an increasein the overlap capacitance.

Further, a MIS transistor (Omega-Fin structure MIS transistor) having anisland-form semiconductor structure surrounded by a gate electrodeexcept the central portion of the undersurface of the island-formsemiconductor structure is proposed in a document 2 (Fu-Liang Yang etal., “25 nm CMOS Omega FETs”, IEDM 2002, 10. 3, pp. 255-258). The MIStransistor is formed as follows. First, an island-form semiconductorstructure is formed on a buried oxide film. Then, the buried oxide filmis etched with the island-form semiconductor structure used as a mask toform a depression portion in the buried oxide film. At this time, theburied oxide film under the end portion of the island-form semiconductorstructure is also etched to from an undercut portion under theisland-form semiconductor structure. Next, a gate electrode materialfilm is formed on the entire surface containing the undercut portion andthe gate electrode material film is patterned to form a gate electrodewhich crosses the island-form semiconductor structure.

In the above proposal, the gate electrode is not formed in a positioncorresponding to the undercut portion under the source and drainregions. That is, unlike the proposal of the document 1, the gateelectrode has no extension portion under the source and drain regions.When the source/drain region is formed by ion implantation, the distancebetween the source and drain regions is generally longer in the lowerportion of the island form semiconductor structure than in the upperportion thereof. In the document 2, since the gate electrode has noextension portion under the source and drain regions, offsets occurbetween the gate electrode and the source region and between the gateelectrode and the drain region to significantly degrade thecharacteristics of the MIS transistor. Further, in the above proposal,since the undercut portion is formed in the entire portion under theisland-form semiconductor structure, it is difficult to sufficientlyfixedly hold the island-form semiconductor structure and there occurs aproblem that the island-form semiconductor structure will fall down inthe manufacturing process.

Thus, from the viewpoint of preventing occurrence of the punch-throughphenomenon between the source and drain, Gate-All-Around structure MIStransistors and Omega-Fin structure MIS transistors are proposed.However, conventional MIS transistors with the above structures have aproblem that the positional relationship between the gate electrode andthe source/drain region cannot be optimized. Thus, it is difficult toattain a semiconductor device which has excellent characteristics andreliability.

BRIEF SUMMARY OF THE INVENTION

A semiconductor device according to a first aspect of the inventioncomprises an underlying insulating film having a depression; asemiconductor structure which includes a first semiconductor portionhaving a portion formed on the underlying insulating film and a firstoverlap portion which overlaps the depression and containing an impurityelement for source/drain, a second semiconductor portion having aportion formed on the underlying insulating film and a second overlapportion which overlaps the depression and is disposed to face the firstoverlap portion and containing an impurity element for source/drain, anda third semiconductor portion disposed between the first and secondsemiconductor portions and having a portion disposed above thedepression, wherein overlap width of the first overlap portion andoverlap width of the second overlap portion are equal to each other; agate electrode including a first electrode portion covering upper andside surfaces of the third semiconductor portion and a second electrodeportion formed in the depression; and a gate insulating film interposedbetween the semiconductor structure and the gate electrode.

A method of manufacturing a semiconductor device according to a secondaspect of the invention comprises forming a semiconductor structurewhich includes a first semiconductor portion, a second semiconductorportion and a third semiconductor portion disposed between the first andsecond semiconductor portions, on an underlying insulating film; forminga dummy structure covering upper and side surfaces of the thirdsemiconductor portion; forming an insulating portion covering a surfaceof the first semiconductor portion, a surface of the secondsemiconductor portion and a side surface of the dummy structure;removing the dummy structure to expose the third semiconductor portionand the underlying insulating film under the dummy structure; forming adepression in the underlying insulating film by etching an exposedportion and a portion adjacent to the exposed portion of the underlyinginsulating film; and forming a gate electrode with a gate insulatingfilm interposed between the third semiconductor portion and the gateelectrode, the gate electrode including a first electrode portioncovering upper and side surfaces of the third semiconductor portion anda second electrode portion formed in the depression.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a perspective view schematically showing the basicconfiguration of a semiconductor device according to a first embodimentof this invention;

FIG. 2 is a plan view schematically showing the basic configuration ofthe semiconductor device according to the first embodiment of thisinvention;

FIGS. 3A to 3C are cross-sectional views each schematically showing thebasic configuration of the semiconductor device according to the firstembodiment of this invention;

FIGS. 4A to 4C are cross-sectional views showing part of a manufacturingprocess of the semiconductor device according to the first embodiment ofthis invention;

FIGS. 5A to 5C are cross-sectional views showing part of themanufacturing process of the semiconductor device according to the firstembodiment of this invention;

FIGS. 6A to 6C are cross-sectional views showing part of themanufacturing process of the semiconductor device according to the firstembodiment of this invention;

FIGS. 7A to 7C are cross-sectional views showing part of themanufacturing process of the semiconductor device according to the firstembodiment of this invention;

FIGS. 8A to 8C are cross-sectional views showing part of themanufacturing process of the semiconductor device according to the firstembodiment of this invention;

FIGS. 9A to 9C are cross-sectional views showing part of themanufacturing process of the semiconductor device according to the firstembodiment of this invention;

FIGS. 10A to 10C are cross-sectional views showing part of themanufacturing process of the semiconductor device according to the firstembodiment of this invention;

FIGS. 11A to 11C are cross-sectional views showing part of themanufacturing process of the semiconductor device according to the firstembodiment of this invention;

FIGS. 12A to 12C are cross-sectional views showing part of themanufacturing process of the semiconductor device according to the firstembodiment of this invention;

FIGS. 13A to 13C are cross-sectional views showing part of themanufacturing process of the semiconductor device according to the firstembodiment of this invention;

FIGS. 14A to 14C are cross-sectional views showing part of themanufacturing process of the semiconductor device according to the firstembodiment of this invention;

FIGS. 15A and 15B are cross-sectional views showing a modification ofthe manufacturing process of the semiconductor device according to thefirst embodiment of this invention;

FIG. 16 is a cross-sectional view showing a modification of themanufacturing process of the semiconductor device according to the firstembodiment of this invention;

FIG. 17 is a perspective view schematically showing the basicconfiguration of a semiconductor device according to a second embodimentof this invention;

FIG. 18 is a plan view schematically showing the basic configuration ofthe semiconductor device according to the second embodiment of thisinvention;

FIGS. 19A to 19D are cross-sectional views each schematically showingthe basic configuration of the semiconductor device according to thesecond embodiment of this invention;

FIG. 20 is a plan view schematically showing one example of the basicconfiguration of a semiconductor device according to a third embodimentof this invention;

FIG. 21 is a plan view schematically showing another example of thebasic configuration of the semiconductor device according to the thirdembodiment of this invention;

FIG. 22 is a plan view schematically showing one example of the basicconfiguration of a semiconductor device according to a fourth embodimentof this invention;

FIG. 23 is a plan view schematically showing another example of thebasic configuration of the semiconductor device according to the fourthembodiment of this invention;

FIG. 24 is a cross-sectional view schematically showing theconfiguration of a semiconductor device according to a fifth embodimentof this invention; and

FIG. 25 is a cross-sectional view schematically showing theconfiguration of a semiconductor device according to a sixth embodimentof this invention.

DETAILED DESCRIPTION OF THE INVENTION

There will now be described embodiments of this invention with referenceto the accompanying drawings.

Embodiment 1

FIG. 1 is a perspective view schematically showing the basicconfiguration of a semiconductor device according to a first embodimentof this invention and FIG. 2 is a plan view showing the semiconductordevice of FIG. 1. FIG. 3A is a cross sectional view taken along the A-A′line of FIG. 2, FIG. 3B is a cross sectional view taken along the B-B′line of FIG. 2 and FIG. 3C is a cross sectional view taken along theC-C′ line of FIG. 2. In FIG. 1, for easy understanding of the structure,the gate electrode is shown separately from the other structure, but inpractice, the gate electrode is formed in contact with the otherstructure. Further, in FIG. 1 and FIGS. 3A to 3C, contacts and wiringsshown in FIG. 2 are omitted.

A buried oxide film (BOX film) 102 having a depression portion 120 isformed as a underlying insulating film on a p-type silicon substrate(semiconductor substrate) 101 with an impurity concentration ofapproximately 5×10¹⁵ cm⁻³.

An island-form semiconductor structure 103 formed of single crystalsilicon is formed on the buried oxide film 102. The semiconductorstructure 103 has a semiconductor portion 103 a, a semiconductor portion103 b and a semiconductor portion 103 c disposed between thesemiconductor portions 103 a and 103 b. The width of the semiconductorstructure 103 in the channel width direction is approximately 20 nm andthe height thereof is approximately 20 nm. Impurities of lowconcentration (approximately 5×10¹⁷ cm⁻³ or lower) are contained in thechannel forming region of a transistor. Further, source and drainregions (source and drain regions 111 a and 111 b of low concentration,source and drain regions 113 a and 113 b of high concentration) areformed on both sides of the channel forming region.

A gate electrode 116 has an electrode portion 116 a disposed to coverthe upper and side surfaces of the semiconductor portion 103 c and anelectrode portion 116 b formed in the depression portion 120 of theburied oxide film 102. The semiconductor structure 103 is surrounded bythe electrode portions 116 a and 116 b and a region surrounded by theelectrode portion 116 a corresponds to the semiconductor portion 103 c.Further, a gate insulating film 115 is disposed between the gateelectrode 116 and the semiconductor structure 103.

Silicon nitride films 110 and silicon oxide films 112 are formed as sidewall insulating films on both sides of the electrode portion 116 a andinterlayer insulating films 114 are formed outside the side wallinsulating films. The surfaces of the semiconductor portions 103 a and103 b are covered with the insulating portions formed of the side wallinsulating films and interlayer insulating films 114. In FIG. 1, thesilicon nitride films 110 and silicon oxide films 112 are not drawn, butthe silicon nitride films 110 and silicon oxide films 112 are formed inregions of the interlayer insulating films 114 which face each otherwith the gate electrode 116 disposed therebetween.

In the present embodiment, as shown in FIG. 1, the depression portion120 formed in the buried oxide film 102 has extension portions 120 a and120 b. Since the extension portions 120 a and 120 b are formed by anisotropic etching process as will be described later, the widths of theextension portions 120 a and 120 b are equal to each other. That is, thewidth of a portion of the semiconductor portion 103 a which overlaps thedepression portion 120 and the width of a portion of the semiconductorportion 103 b which overlaps the depression portion 120 are equal toeach other. Since the depression portion 120 has the extension portions120 a and 120 b and the electrode portion 116 b of the gate electrode116 is aligned with the depression portion 120, the length Lb of theelectrode portion 116 b in the channel length direction is greater thanthe length La of the electrode portion 116 a in the channel lengthdirection. Further, the width Lb1 of an extension portion 116 b 1 of theelectrode portion 116 b in the channel length direction and the widthLb2 of an extension portion 116 b 2 in the channel length direction areequal to each other.

As shown in FIG. 3B, the distance between the source region 111 a andthe drain region 111 b becomes longer in a portion which is separatedfarther away from the upper portion of the semiconductor structure 103towards the lower portion. Therefore, if the length of the gateelectrode in the channel length direction is kept constant, there occursa possibility that an offset structure will be made in a lower region ofthe semiconductor structure 103. In the present embodiment, since thegate electrode 116 has the extension portions 116 b 1 and 116 b 2,formation of the offset structure can be prevented. Further, in thepresent embodiment, the width of the extension portion 120 a of thedepression portion 120 and the width of the extension portion 120 b aremade equal to each other, that is, the width Lb1 of the extensionportion 116 b 1 of the gate electrode 116 and the width Lb2 of theextension portion 116 b 2 are made equal to each other. Therefore, theoverlap capacitance between the gate electrode and the source region andthe overlap capacitance between the gate electrode and the drain regioncan be made equal to each other. Further, as will be described later,since the depression portion 120 is not dependent on the lithographyprocess, it can be formed without taking the margin for the alignmenterror into consideration. Therefore, the overlap capacitance itself canbe reduced. Thus, in the present embodiment, the positional relationshipbetween the gate electrode and the source/drain region can be optimizedin all of transistors formed in the same wafer or in the same integratedcircuit chip and a semiconductor device having excellent characteristicsand reliability can be attained.

Further, the channel region can be completely depleted by the gateelectrode 116 and occurrence of the punch-through phenomenon between thesource and drain can be prevented by setting the width of thesemiconductor structure 103 in the channel width direction equal to orless than approximately 20 nm. In addition, since the impurityconcentration of the channel region can be set lower than that in thenormal planar type MIS transistor, the decrease of mobility in thechannel region due to high concentration impurities can be suppressed.

Further, in the present embodiment, the edge portions of thesemiconductor portions 103 a and 103 b of the semiconductor structure103 are formed in contact with the buried oxide film (underlyinginsulating film) 102. Therefore, the semiconductor structure 103 can besufficiently fixedly held and a problem that the semiconductor structurewill fall down in the manufacturing process can be prevented.

A manufacturing method of the semiconductor device according to thepresent embodiment is explained below with reference to FIGS. 4A, 4B and4C to FIGS. 14A, 14B and 14C. FIGS. 4A to 14A correspond to the crosssections taken along the A-A′ line of FIG. 2, FIGS. 4B to 14B correspondto the cross sections taken along the B-B′ line of FIG. 2, and FIGS. 4Cto 14C correspond to the cross sections taken along the C-C′ line ofFIG. 2.

First, as shown in FIGS. 4A, 4B and 4C, an SOI substrate having a (100)p-type silicon substrate (semiconductor substrate) 101 with an impurityconcentration of approximately 5×10¹⁵ cm⁻³, a buried oxide film (BOXfilm: underlying insulating film) 102 with a thickness of approximately200 nm and a (100) p-type silicon layer (semiconductor layer) 103 withan impurity concentration of approximately 5×10¹⁵ cm⁻³ is prepared. Asthe SOI substrate, an SOI substrate obtained by subjecting a substrateformed by an SIMOX method to a thermal oxidation process and wet etchingprocess and reducing the thickness thereof or an SOI substrate formed byuse of a laminating method may be used. It is preferable to set thethickness of the silicon layer 103 to approximately 10 nm to 30 nm. Inthis example, it is set to approximately 2.0 nm. It is preferable to setthe uniformity of the thickness of the silicon layer 103 within ±5% inthe entire portion of the wafer. The plane direction of the siliconlayer 103 is not necessarily set to the same as the plane direction ofthe silicon substrate 101 and a plane direction which causes the bestelement characteristic can be set. For example, two silicon substratesmay be laminated with an angle of 45 degrees made therebetween and thenthe silicon layer 103 may be formed by reducing the thickness of one ofthe two silicon substrates. Further, a glass substrate can be usedinstead of the silicon substrate 101.

Next, an impurity layer of low concentration (concentration ofapproximately 5×10¹⁷ cm⁻³) is formed in the channel forming region ofthe transistor by ion implantation. In this case, however, since thechannel of the transistor of the present embodiment can be completelydepleted, it is difficult to control the threshold voltage even if animpurity layer is formed in the channel forming region. Therefore, theion-implantation process for formation of the channel impurity layer canbe omitted.

Next, a thermal oxide film 104 with a thickness of approximately 2 nmand a silicon nitride film 105 with a thickness of approximately 50 nmare formed. Then, a resist pattern (not shown) is formed on the siliconnitride film 105 by the lithography process. In this example, the resistpattern is formed by use of an electron beam exposure process. Further,the thermal oxide film 104 and silicon nitride film 105 are processedwith the resist pattern used as a mask and a mask layer formed of thethermal oxide film 104 and silicon nitride film 105 is formed.

Next, the silicon layer is etched by using the thus formed mask layer asa mask to form an island-form semiconductor structure (Fin structure)103. The height (thickness) and width of the semiconductor structure 103are set to approximately 20 nm. Since damage caused at the etching timemay be left behind on the side surface of the semiconductor structure103 in some cases, a process for eliminating the etching damage isperformed. For example, the side surface of the semiconductor structure103 is oxidized to form a thin oxide film (approximately 1 nm) and aprocess for eliminating the thin oxide film is performed. Further, theetching damage can be eliminated by use of the ashing process and wetprocess. If the etching process which causes less etching damage isused, the above process can be omitted. The side surface of thesemiconductor structure 103 may be vertically set, but may be inclinedwith an angle of approximately 85 degrees, for example.

After the semiconductor structure 103 is formed, a thermal oxide film151 may be formed by a high-temperature thermal oxidation process ofapproximately 1000° C. as shown in FIGS. 15A and 15B. Thus, the cornerportion of the semiconductor structure 103 can be rounded with a radiusof approximately 5 nm. By rounding the corner portion of thesemiconductor structure 103, concentration of the electric field in thecorner portion can be alleviated and it becomes easy to control thethreshold voltage.

Next, as shown in FIGS. 5A, 5B and 5C, the side surface of thesemiconductor structure 103 is covered with an oxide film (not shown).As the oxide film, an oxide film formed in the etching damageeliminating process can be used. Then, the silicon nitride film 105 isremoved by use of hot phosphoric acid. Further, the thermal oxide film104 is removed by the wet etching process. After this, an oxide film 106with a thickness of approximately 2 nm is formed as a dummy gateinsulating film on the upper and side surfaces of the semiconductorstructure 103. For formation of the oxide film 106, it is preferable touse an oxygen radical oxidation method which permits an oxide film ofhigh quality to be obtained at low temperatures (for example,approximately 700° C.). The buried oxide film 102 is slightly etched inthe etching process for the thermal oxide film 104. The etchingcondition is adjusted so as to prevent the buried oxide film 102 underthe lower surface of the semiconductor structure 103 from being erodedby etching. After this, a polysilicon film 108 with a thickness ofapproximately 30 nm is deposited on the entire surface.

Next, as shown in FIGS. 6A, 6B and 6C, the polysilicon film 108 is madeflat by a CMP (Chemical Mechanical Polishing) process, for example.

Then, as shown in FIGS. 7A, 7B and 7C, a silicon oxide film 109 with athickness of approximately 50 nm is formed as a mask layer on the flatpolysilicon film 108 by the CVD method.

Next, as shown in FIGS. 8A, 8B and 8C, the silicon oxide film 109 isetched by using a resist pattern (not shown) corresponding to a gateelectrode pattern as a mask. After the resist pattern is removed, adummy gate electrode 108 is formed by etching the polysilicon film 108with the patterned silicon oxide film 109 used as a mask. Theetching-process is performed in an etching condition of high selectiveratio so as to leave the silicon oxide film 106 on the upper and sidesurfaces of the semiconductor structure 103. A region directly below thethus formed dummy gate electrode 108 corresponds to the semiconductorportion 103 c of the semiconductor structure 103.

Next, as shown in FIGS. 9A, 9B and 9C, a silicon nitride film 110 with athickness of approximately 10 nm is deposited on the side surfaces ofthe dummy gate electrode 108 and silicon oxide film 109. Then,impurities are ion-implanted with the silicon oxide film 109 and dummygate electrode 108 used as a mask to form a source region 111 a anddrain region 111 b of low impurity concentration in the semiconductorstructure 103. After this, a silicon oxide film 112 with a thickness ofapproximately 10 nm is deposited. Next, the silicon oxide film 112 andsilicon nitride film 110 are etched by an RIE process. As a result,portions of the silicon oxide film 112 and silicon nitride film 110 areleft behind along the side wall of the dummy gate electrode 108. At thistime, the silicon oxide film 112 and silicon nitride film 110 are alsoleft behind on the side wall of the semiconductor structure 103. Then,an ion implantation process of arsenic (As) ions is performed to form asource region 113 a and drain region 113 b of high impurityconcentration in the semiconductor structure 103. In this example, bothof the source/drain regions (extension regions) of low impurityconcentration and the source/drain regions of high impurityconcentrations are formed, but it is also possible to use singlesource/drain regions.

Next, as shown in FIGS. 10A, 10B and 10C, a silicon oxide film 114(interlayer insulating film) with a thickness of approximately 100 nm isdeposited on the entire surface by the CVD method. Then, a heattreatment of 1000° C. for about 10 seconds is performed by an RTA (RapidThermal Annealing) method. The heat treatment is also used as anactivation process for the source/drain regions. In the heat treatment,the heat treatment temperature is set so as to prevent impurities of thesource/drain regions from being excessively diffused and prevent thechannel length from becoming excessively small. After this, the siliconoxide film 114 is made flat by the CMP method to expose the surface ofthe dummy gate electrode 108.

Next, as shown in FIGS. 11A, 11B and 11C, the exposed dummy gateelectrode 108 is selectively removed by a chemical dry etching processusing CF₄ gas and N₂ gas. As a result, the surfaces of the buried oxidefilm 102 and silicon oxide film 106 under the dummy gate electrode 108are exposed. The silicon oxide film 112 and silicon nitride film 110formed on the side wall of the dummy gate electrode 108 are scarcelyetched.

Then, the exposed buried oxide film 102 and silicon oxide film 106 areetched by a wet etching process using, for example, dilute hydrofluoricacid to form a depression portion 120 in the buried oxide film 102. Theside surface of the silicon oxide film 114 is protected by the siliconnitride film 110 and is not etched. Since the etching process is anisotropic etching process, the etching proceeds in depth and lateraldirections and an adjacent portion of the exposed buried oxide film 102is also etched. Therefore, the etching proceeds to a region directlyunder the semiconductor structure 103 and the depression portion 120 isformed in the entire portion under the semiconductor portion 103 c.Further, extension portions 120 a and 120 b are formed under thesemiconductor portions 103 a and 103 b. The widths of the extensionportions 120 a and 120 b in the channel length direction are set equalto each other.

In the present embodiment, since the depression portion 120 is formed inthe entire portion under the semiconductor portion 103 c, it isnecessary to set the etching width in the lateral direction (the widthsof the extension portions 120 a and 120 b) to at least W/2 in the casewhere the width of the semiconductor structure 103 is set to W. Further,in order to form the depression portion 120 in the entire portion underthe semiconductor portion 103 c without fail, the etching amount is soset to make the etching width greater than W/2. However, if the etchingwidth is set excessively, the overlap width of the gate electrode andthe source/drain region will become great when the gate electrode isformed in the depression portion 120. Therefore, it is desirable to setthe etching width equal to or less than W. In the present embodiment,since the width W of the semiconductor structure 103 is 20 nm, theetching width is set to 15 nm. That is, the widths of the extensionportions 120 a and 120 b are set to 15 nm.

Next, as shown in FIGS. 12A, 12B and 12C, a silicon oxide film with athickness of approximately 1.5 nm is formed at a temperature ofapproximately 700° C. on the exposed surface of the semiconductorstructure 103 by a radical oxidation method. Further, the silicon oxidefilm surface is nitrided by a radical nitriding method to form a gateinsulating film 115 which is formed of a silicon oxynitride film (SiONfilm). By using the radical oxidation method, a silicon oxide film whichis less irregular can be formed on the surface of the semiconductorstructure 103. Therefore, a lowering in the channel mobility caused bychannel interface scattering can be suppressed. Further, in the radicaloxidation process, since the film thickness of the silicon oxide film isdetermined by the temperature, a variation in the film thickness of thesilicon oxide film can be suppressed.

As the gate insulating film 115, a high dielectric constant film formedof a metal oxide such as a tantalum oxide film (Ta₂O₅ film), an HfSiONfilm formed by adding nitrogen to an Hf silicate film, an HfO₂ film, aZr silicate film, or the like can be used. The relative dielectricconstant εr of the Ta₂O₅ film, for example, is approximately 20 to 27and is considerably greater than the relative dielectric constant εr(approximately 3.9) of the silicon oxide film. Therefore, the equivalentoxide film thickness can be set equal to or less than 1 nm. Further, asilicon oxide film with a thickness of approximately 0.5 nm may beformed to reduce the interface state density and a high dielectricconstant film such as a Ta₂O₅ film may be formed on the silicon oxidefilm. In addition, a high dielectric constant film can be formed by useof an ALD (Atomic Layer Deposition) CVD method. For example, an SiO₂film (relative dielectric constant: approximately 3.9) with a thicknessof approximately 0.3 nm by use of the ALD method, an HfO₂ film (relativedielectric constant: approximately 25) with a thickness of approximately1 nm by use of the ALD method, and an Si₃N₄ film (relative dielectricconstant: approximately 7.0) with a thickness of approximately 0.3 nm byuse of the ALD method may be sequentially formed at low temperatures(approximately 200 to 500° C.). Further, after formation of the films,an anneal process of approximately 400° C. may be performed.

Next, a polysilicon film 116 is deposited to a thickness ofapproximately 60 nm on the entire surface at a temperature ofapproximately 700° C. by an LPCVD method using silane gas, for example.The polysilicon film 116 is also formed in the depression portion 120under the semiconductor structure 103. N-type impurities (As, P or thelike) with a concentration of approximately 3×10²⁰ cm⁻³ are doped intothe polysilicon film of an N-channel transistor region and P-typeimpurities (B or the like) with a concentration of approximately 3×10²⁰cm⁻³ are doped into the polysilicon film of a P-channel transistorregion by the ion implantation process, for example. Further, theactivation process is performed at 900° C. for approximately 10 secondsby RTA.

In order to lower the resistance of the gate electrode, a metal film(TiN film, Mo film, W film, Al film or the like) or a metal silicidefilm (nickel silicide (NiSi) film, cobalt silicide (CoSi) film, titaniumsilicide (TiSi₂) film or the like) may be used as the gate electrode.Further, a stack film of a polysilicon film and metal film or a stackfilm of a polysilicon film and metal silicide film may be used as thegate electrode. In addition, the alignment state of the gate electrodematerial such as TiN can be adjusted and the threshold voltage of thetransistor can be adjusted by using a difference between the workfunctions of the gate insulating film and gate electrode. After N-typeimpurities are doped into the polysilicon film of the N-channeltransistor region and P-type impurities are doped into the polysiliconfilm of the P-channel transistor region, a Ni film is formed on thepolysilicon film and a Ni silicide film is formed by performing the heattreatment to react the Ni film with the polysilicon film. Thus, optimumwork functions can be given to the gate electrodes of the N-channel andP-channel transistors. In this case, the work function of the Nisilicide electrode of the N-channel transistor can be set toapproximately 4.2 eV and the work function of the Ni silicide electrodeof the P-channel transistor can be set to approximately 4.9 eV.

Next, as shown in FIGS. 13A, 13B and 13C, the polysilicon film 116 issubjected to the flattening process by the CMP method. In the flatteningprocess, a portion of the polysilicon film 116 which lies on theinterlayer insulating film 114 is removed. Thus, a gate electrode 116which surrounds the semiconductor structure 103 is formed. As shown inFIG. 16, the polysilicon film 116 may be patterned with the resistpattern 161 used as a mask. In this case, a T-shaped gate electrode 116can be formed and the wiring resistance of the gate electrode can belowered.

Next, as shown in FIGS. 14A, 14B and 14C, a silicon oxide film isdeposited as an interlayer insulating film 117 on the entire surface bythe CVD method. Then, contact holes are formed in the interlayerinsulating film 117. Further, the contact holes are filled with a Wfilm, Al film or TiN film/Ti film to form contact plugs 118. After this,an Al wiring 119 connected to the contact plugs 118 is formed. Then, apassivation film (not shown) is formed on the entire surface.

Thus, according to the manufacturing method of the present embodiment,the buried oxide film 102 is exposed by removing the dummy gateelectrode 108 and the exposed portion of the buried oxide film 102 isetched and removed to form the depression portion 120. Since the buriedoxide film 102 is isotropically etched, the depression portion 120extends to under the semiconductor portions 103 a and 103 b of thesemiconductor structure 103 and the widths of the extension portions 120a and 120 b become equal to each other. Therefore, the width in thechannel direction of the electrode portion 116 b of the gate electrode116 formed in the depression portion 120 can be increased and theoverlap width of the gate electrode and the source region and theoverlap width of the gate electrode and the drain region can be madeequal to each other. As a result, as is already described, thepositional relationship between the gate electrode and the source/drainregion can be optimized for all transistors formed in the same wafer orthe same integrated circuit chip. Thus, a semiconductor device which isexcellent in characteristics and reliability can be attained.

Further, in the step after the semiconductor structure 103 is formed,the edge portions of the semiconductor portions 103 a and 103 b of thesemiconductor structure 103 are formed in contact with the buried oxidefilm 102. Therefore, the semiconductor structure 103 can be sufficientlyfixedly held during the manufacturing process and occurrence of aproblem that the semiconductor structure 103 will fall down in themanufacturing process can be prevented.

Embodiment 2

FIG. 17 is a perspective view showing the configuration of asemiconductor device according to a second embodiment of this inventionand FIG. 18 is a plan view of the semiconductor device shown in FIG. 17.FIG. 19A is a cross sectional view taken along the A-A′ line of FIG. 18,FIG. 19B is a cross sectional view taken along the B-B′ line of FIG. 18,FIG. 19C is a cross sectional view taken along the C-C′ line of FIG. 18,and FIG. 19D is a cross sectional view taken along the D-D′ line of FIG.18. In FIG. 17, for easy understanding of the structure, the gateelectrode is drawn to be separated from the other structure, but inpractice, the gate electrode is formed in contact with the otherstructure. Further, in FIGS. 17 and 19A to 19D, contacts and wiringsshown in FIG. 18 are omitted. The basic configuration of the presentembodiment is the same as that of the first embodiment. The samereference numbers are attached to the same constituents as those of thefirst embodiment and the explanation therefor is omitted.

In the first embodiment, the electrode portion 116 b of the gateelectrode 116 is formed to cover the entire portion of the undersurfaceof the semiconductor portion 103 c of the semiconductor structure 103.However, in the present embodiment, the electrode portion 116 b isformed to partly cover the undersurface of the semiconductor portion 103c. That is, the gate electrode 106 does not completely surround thesemiconductor portion 103 c and the gate electrode 106 is discontinuousin a region under the central portion of the semiconductor portion 103c. The other basic configuration is the same as that in the firstembodiment.

The basic manufacturing method of the semiconductor device of thepresent embodiment is also the same as in the first embodiment. However,in the present embodiment, in the step of FIGS. 11A, 11B and 11C shownin the first embodiment, the buried oxide film 102 is left behind in thecentral portion of the semiconductor portion 103 c without forming thedepression portion 120 in the entire portion under the semiconductorportion 103 c when the buried oxide film 102 is etched and removed toform the depression portion 120. Therefore, when the width of thesemiconductor structure 103 is set to W, it is possible to set theetching width (the widths of the extension portions 120 a and 120 b ofthe depression portion 120) less than W/2.

As described above, since the basic configuration of the semiconductordevice of the present embodiment and the basic manufacturing methodthereof are the same as those of the first embodiment, the same effectas that of the first embodiment can be attained. Further, in the presentembodiment, since the widths of the extension portions 120 a and 120 bof the depression portion 120 can be made small, the overlap width ofthe gate electrode and the source/drain region can be made small and theoverlap capacitance can be reduced.

Embodiment 3

FIGS. 20 and 21 are a plan view showing an example of the configurationof a semiconductor device according to the present embodiment. The basicconfiguration of the semiconductor device shown in FIG. 20 correspondsto the configuration of the first embodiment. Further, the basicconfiguration of the semiconductor device shown in FIG. 21 correspondsto the configuration of the second embodiment. Therefore, detailedexplanation of the respective constituents is omitted.

In the first and second embodiments, the shape of the semiconductorstructure 103 is a rectangular parallelepiped form and the width of thesemiconductor structure 103 in the channel width direction is uniform.However, in the present embodiment, the width of the semiconductorstructure 103 in the channel width direction is greater in thesemiconductor portions 103 a and 103 b than in the semiconductor portion103 c. Therefore, it is possible to easily form the contact holes forthe source/drain regions and suppress a rise and a variation in thecontact resistance.

Embodiment 4

FIGS. 22 and 23 are a plan view showing an example of the configurationof a semiconductor device according to the present embodiment. The basicconfiguration of the semiconductor device shown in FIG. 22 correspondsto the configuration of the first embodiment. Further, the basicconfiguration of the semiconductor device shown in FIG. 23 correspondsto the configuration of the second embodiment. Therefore, detailedexplanation of the respective constituents is omitted.

In the present embodiment, semiconductor structures 103 as shown in FIG.20 or 21 are arranged in parallel, semiconductor portions 103 c areseparately disposed and semiconductor portions 103 a and 103 b arecommonly used. A gate electrode 116 is commonly used and one transistoris configured by the configuration shown in the drawing.

With the above configuration, the effective channel width of thetransistor can be increased without significantly increasing theoccupied area of the transistor. Therefore, a high performancesemiconductor integrated circuit can be formed with high density.

Embodiment 5

FIG. 24 is a cross sectional view showing one example of a configurationobtained when the transistor structure shown in the first or secondembodiment is applied to a DRAM having a trench type capacitorstructure.

In FIG. 24, a reference symbol 201 denotes a P-type silicon substrate,202 an N well (plate electrode), 203 a buried oxide film (BOX film), 204an n⁻-type diffusion layer, 205 an n⁺-type polysilicon layer, 206 acapacitor insulating film, 207 a Collar insulating film, 208 anisolation insulating film, 209 a buried insulating film, and 210 a sidewall contact. Further, a reference symbol 211 denotes a source/drainregion, 212 a channel forming region, 213 a gate insulating film, 214 apolysilicon film used as a gate electrode, and 215 a silicide film. Areference symbol 216 denotes a silicon nitride film formed on thesilicide film 215, 217 an interlayer insulating film, 218 a bit linecontact, and 219 a bit line. In addition, a reference symbol 220 denotesa 1-bit memory cell region.

As shown in FIG. 24, the source/drain region 211 and the storageelectrode (n⁺-type polysilicon layer 205) of the capacitor areelectrically connected to each other at the upper side surface of thetrench via the side wall contact 210. In the conventional planar typeMIS transistor structure, the side wall contact region is formed deeperin the vertical direction, which prevents the source/drain region frombeing made thin.

By using the MIS transistor structure of the present embodiment, even ifthe diffusion layer from the side wall contact gives an influence to thesource/drain region and the source/drain region is formed deeper, theinfluence can be fully suppressed by the gate electrode formed on theside surface of the semiconductor structure. That is, the short channeleffect caused by extension of the diffusion layer from the side wallcontact can be suppressed.

Thus, by applying the transistor structure as shown in the first orsecond embodiment to a DRAM having a trench type capacitor structure, ahigh performance DRAM can be attained.

Embodiment 6

FIG. 25 is a cross sectional view showing one example of a configurationobtained when the transistor structure shown in the first or secondembodiment is applied to a DRAM having a stack type capacitor structure.

In FIG. 25, a reference symbol 301 denotes a P-type silicon substrate,302 a buried oxide film (BOX film), 303 an isolation insulating film,304 a buried insulating film, 305 a source/drain region, 306 a channelforming region, and 307 a gate insulating film. A reference symbol 308denotes a polysilicon film used as a gate electrode and 309 denotes asilicide film. A reference symbol 310 denotes a silicon nitride filmformed on the silicide film 309. A reference symbol 311 denotes aninterlayer insulating film, 312 a bit line contact, 313 a bit line, and314 and 315 SN (storage node) contacts. Further, a reference symbol 316denotes an SN electrode, 317 a capacitor insulating film, 318 a plateelectrode, and 319 an interlayer insulating film. A reference symbol 320denotes a 1-bit memory cell region.

In the present embodiment, the SN contact 314 and the bit line contact312 formed by use of polysilicon are formed to extend to above the gateelectrode. In the conventional planar type MIS transistor structure,since the contact region is made fine, it is difficult to sufficientlyreduce the contact resistance. In the MIS transistor structure of thepresent embodiment, since the contact can be formed by utilizing notonly the plane portion but also the side surface portion, the contactresistance can be reduced.

Further, in the stack type capacitor using a high dielectric constantfilm such as a BST film, STO film or Ta₂O₅ film, the capacitor is formedafter the MIS transistor is formed. However, at the time of capacitorformation, a high-temperature process such as a crystallizationannealing process at approximately 750° C. is performed. Therefore, thesource/drain diffusion layer is formed deeper and there occurs a problemthat the short channel effect occurs. By using the MIS transistorstructure of the present embodiment, the short channel effect can besufficiently suppressed. That is, the short channel effect caused byextension of the source/drain diffusion layer in the capacitor formationprocess can be sufficiently suppressed.

In the example shown in the drawing, the capacitor is formed above thebit line, but the bit line can be formed above the capacitor or thecapacitor can be formed above the wiring.

Thus, by applying the transistor structure as shown in the first orsecond embodiment to a DRAM having a stack type capacitor structure, ahigh performance DRAM can be attained.

In each of the above embodiments, the N-channel transistor is mainlyexplained as an example. However, the configuration and themanufacturing method explained in each of the above embodiments can beapplied in the same manner when a P-channel transistor is used. Further,the MIS transistor explained in each of the above embodiments and anormal planar type MIS transistor may be formed within the same wafer orin the same chip. In addition, a plurality of MIS transistors explainedin each of the above embodiments can be used to configure a flashmemory, SRAM, DRAM, various types of logic circuits, CPU or the like.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1-11. (canceled)
 12. A method of manufacturing a semiconductor devicecomprising: forming a semiconductor structure which includes a firstsemiconductor portion, a second semiconductor portion and a thirdsemiconductor portion disposed between the first and secondsemiconductor portions, on an underlying insulating film; forming adummy structure covering upper and side surfaces of the thirdsemiconductor portion; forming an insulating portion covering a surfaceof the first semiconductor portion, a surface of the secondsemiconductor portion and a side surface of the dummy structure;removing the dummy structure to expose the third semiconductor portionand the underlying insulating film under the dummy structure; forming adepression in the underlying insulating film by etching an exposedportion and a portion adjacent to the exposed portion of the underlyinginsulating film; and forming a gate electrode with a gate insulatingfilm interposed between the third semiconductor portion and the gateelectrode, the gate electrode including a first electrode portioncovering upper and side surfaces of the third semiconductor portion anda second electrode portion formed in the depression.
 13. The methodaccording to claim 12, wherein the second electrode portion entirelycovers a lower surface of the third semiconductor portion.
 14. Themethod according to claim 12, wherein the second electrode portionpartly covers a lower surface of the third semiconductor portion. 15.The method according to claim 12, further comprising introducing animpurity element for source/drain into the first and secondsemiconductor portions.
 16. The method according to claim 12, whereinthe underlying insulating film is isotropically etched in forming thedepression in the underlying insulating film.